1. Field of the Invention
The present invention relates to the manufacture of high-frequency bipolar integrated circuits and more particularly to the manufacture of the extrinsic base of an NPN transistor in a high-frequency bipolar technology.
2. Discussion of the Related Art
A manufacturing method of high-frequency bipolar integrated circuits combines many steps to be performed in order to make an integrated circuit out of a silicon wafer. Thus, the method includes the steps of doping by ion implantation or by pre-deposition, photolithography, thermal oxidation, epitaxial growth, diffusion and plasma etching or chemical etching.
These methods of manufacture are being constantly improved to increase the density of integration of the integrated circuits as well as their electrical performance characteristics.
One known standard method of manufacture, describing chiefly the steps needed to make an NPN transistor, is described below in reference to FIG. 1. The figure does not, however, show all the cleaning steps which have no effect on the structure of the layers but which are essential to obtain a high manufacturing output.
FIG. 1 shows a sectional view of an NPN transistor, and is labeled to identify the different zones and layers of an NPN transistor made by means of high-frequency bipolar technology. The starting material is a P type semiconductor substrate. The method includes the following steps:
a) the doping of the substrate 1 by ion implantation to form a highly doped N type buried layer 2; PA1 b) epitaxial growth of a weakly doped N type layer 3; PA1 c) post-epitaxial oxidation to form a thin oxide film on the surface of the epitaxial layer followed by the deposition of a silicon nitride film; the oxide film prevents the tensile stress prompted by the nitride film on the epitaxial layer and is also used as a buffer oxide during ion implantation. These two films cannot be seen in FIG. 1 because they are removed at the end of the process; PA1 d) insulation by lateral oxide 4 also called thick LOCOS growth to insulate the components from one another; PA1 e) the creation of a highly doped N type collector well 5 by ion implantation; PA1 f) insulation by anti-channel diffusion, namely the creation of a P type channel 6 under thick oxide 4 by ion implantation to prevent leakage currents between collectors, followed by the diffusion of these channels in the epitaxial layer 3; the diffusion of the collector well is done simultaneously; PA1 g) the definition of so-called active zones in the epitaxial layer 3 by the etching of the silicon nitride layer; PA1 h) the creation of an extrinsic base 7 by the pre-deposition of boron out of boron nitride; the extrinsic base 7 is an active zone of the NPN transistor that sets up the link between an intrinsic base 10 located beneath the emitter zone 9 and a base contact zone 8 connecting the intrinsic base 10 to a first metal layer; the extrinsic base 7 is highly doped in order to reduce the resistance rbb' of the Giacoletto pattern and enable the integrated circuit to work at high frequency; the pre-deposition operation is followed by a step for the diffusion of boron in the epitaxial layer; the step h) will be more particularly described hereinafter in the description; PA1 I) the creation, by ion implantation, of the P type base contact zone 8; this zone is highly doped to obtain efficient ohmic contact between the first metal layer and the remaining part of the base; PA1 j) the creation of the highly doped N type emitter zone 9 by ion implantation; PA1 k) the creation of the P doped intrinsic base 10 by ion implantation; PA1 l) the creation of resistors by ion implantation; following these four operations of ion implantation, a diffusion of dopants is done in the epitaxial layer; PA1 m) the deposition of metal layers 11; these layers enable the connection of the components of the integrated circuit with one another; PA1 n) the deposition of a passivation layer to protect the integrated circuit. PA1 a thin LOCOS oxide growth to protect the active zones of all the components of the wafer; these active zones are for example the extrinsic base of an NPN transistor, the base of a PNP transistor or the zones provided for implanted resistors; PA1 a photoetching operation to remove the thin LOCOS oxide on the extrinsic base zones of the NPN transistors; indeed, the doping by boron pre-deposition concerns only the extrinsic base of the NPN transistor; PA1 a pre-deposition of boron using boron nitride wafers on the entire wafer; during the pre-deposition, an oxide layer and a layer of boron glass are formed on the surface of the doped layer; a first operation of corrosion by means of hydrofluoric acid is used to eliminate the oxide layer; an operation of dilution then brings about the growth of a new oxide layer that absorbs the boron glass; a second operation of corrosion with hydrofluoric acid eliminates this second oxide layer; PA1 a difflusion of the dopants in the silicon followed by a second thin LOCOS oxide growth on the surface of the doped zone.
In considering the different steps of this method of manufacture, it is seen that the doping operations are done either by pre-deposition or by ion implantation. The technique of pre-deposition is the older of the two doping techniques and enables a controlled introduction of dopants into the substrate. However, ion implantation provides for even more precise control of the dose and depth of penetration of the dopants implanted in the substrate.
However, there remains a step of pre-deposition to make the extrinsic base of the NPN transistors. The extrinsic base is an active zone of the NPN transistor and, in this respect, can withstand only a very small rate of defects in its structure. When the substrate or the epitaxial layer is subjected to ion implantation, the crystal lattice is damaged due to atomic collision and becomes amorphous. The defects of the crystal lattice are then very often amplified during the oxidation that follows the step for the diffusion of the dopants of the extrinsic base.
These defects may then lead to electrical problems, especially problems with respect to the base emitter and base-collector breakdown voltages of the NPN transistor.
The step of making the extrinsic base (step h) is therefore generally done by pre-deposition to avoid these electrical problems. This step comprises the following operations:
This step for the making of the extrinsic base of the NPN transistor (step h) requires many passages of the wafers in a conventional oven (with oxide growths, pre-deposition, dilution and diffusion) as well as several operations of cleaning and chemical etching (operations of corrosion with hydrofluoric acid) and is consequently very lengthy.
An aim of the invention is to shorten this step of the manufacture of the extrinsic base of an NPN transistor without having to rearrange the other steps of the method of manufacturing the NPN transistor and having a result that is at least equivalent to that of the conventional technique.